FIG. 1 is a cross-section view of a lateral double-diffused MOSFET (LDMOS) transistor 20 of the prior art. Such LDMOS devices are often used as a high voltage transistor for power MOS applications, for example. Such LDMOS devices are typically formed on a same substrate as low voltage transistors in an integrated circuit.
Referring to the example LDMOS transistor 20 of FIG. 1, a p-type well layer 22 is formed on a substrate 24. An isolation region 26, which includes isolation field oxide 28, defines an active area 30 for the LDMOS transistor 20 shown in FIG. 1. The well layer 22 has a high voltage n-type well region 32 and a high voltage p-type well region 33 formed therein. A well field oxide 34 is formed (e.g., by thermal growth) over the n-type well region 32. The well field oxide 34 of the prior art is usually formed during the same process and at the same level as the isolation field oxide 28. A drain N+ doped region 36 is formed in the n-type well region 32 between the well field oxide 34 and the isolation field oxide 28. A source N+ doped region 38 is formed in the p-type well region 33 and between a gate dielectric 40 and the isolation field oxide 28. Also, a source P+ doped region 42 is formed in the p-type well region 33 between the source N+ doped region 38 and the isolation field oxide 28.
One of the purposes of the well field oxide 34 is to reduce hot carrier effects and increase the on-breakdown voltage level for the LDMOS power device 20. A higher electron field between the drain 36 and gate electrode 44 may cause hot carriers to form between the drain 36 and the gate electrode 44, which may penetrate the gate dielectric 40 and the well field oxide 34. Such hot carrier effects may cause decreased reliability, reduced gate oxide integrity (GOI), and a non-ideal IV operation curve at high voltage levels. For example, an IV operation curve for the LDMOS device 20 of FIG. 1 is shown in FIG. 2. Region 46 in FIG. 2 shows that the IV operation curve becomes non-ideal as the voltage from drain to source (Vds) becomes higher (e.g., above about 60 V). The vertical axis of FIG. 2 is the current from drain to source (Ids) in the LDMOS device 20 of FIG. 1. In 100 V LDMOS technology of the prior art, for example, the curves of lower voltage from gate to source (Vgs) (e.g., at about 10-30 V) have abnormal trends when the Vds is higher, in such cases. Hence, a need exists for a LDMOS device that has a more ideal IV operation curve at higher voltage levels for Vds (e.g., above about 60 V) to provide more reliable operation of the LDMOS device at such levels.